Memory Interface IP
From the beginning of the electronic era, there has been an insatiable need for memory bandwidth. However, with small form factors and thermal limits, energy efficient bandwidth is fast becoming a must in memory sub-systems.
With new applications in AI, 5G, AR, high definition displays etc.. poised to take over the market, memory bandwidth, latency and power are ever increasingly critical parameters in today’s and future SOC’s
From the low power, high data rate LPDDR4x/5 to the compute workhorse DDR4/5 all the way to the insane bandwidth of HBM, Kalatronics will offer high performance, differentiated PPA memory interface PHY across a wide range of end-user applications.
The first design IP from our team will be an LPDDR4x5 Combo PHY whose details are listed below.
Stay tuned for more announcements...
LPDDR4x5 PHY Some Features:
- Support for both LPDDR4x and LPDDR5
- DFI 5.0
- High performance : up to 6400Mbps data rate
- 1:1, 1:2 and 1:4 mode support
- Low power mode and retention
- DFE and FFE support for high speed IO
- DCD correction
- Link ECC
- PHY independent training
- Per-bit deskew
- Internal and external loopback
- Multi-rank and multi-FSP support
- Built in PLL
- Hard macro delivery
- Low latency pipeline